Computer systems comprising a processor; a high capacity, low-speed (relative to the processor speed) main memory; and a low capacity, high-speed (comparable to the processor speed) cache memory are well known in the prior art to reduce effective memory access time for a reasonable cost. Information required by the processor is read from the main memory, provided to the processor, and written into the cache memory. If the same information is again required by the processor, it is read directly from the cache memory to avoid the processing time delay which is encountered when reading the main memory. If the cache memory is filled and the processor requires information which is not stored in the cache memory, the required information must be obtained from the main memory and a storage location in the cache memory must be identified for storing this new information. A satisfactory cache storage location for storing new information is identified by one of several commonly used replacement algorithms, e.g., random replacement and least recently used. The replacement of information in the cache memory provides current information in the cache memory for use by the processor.
Subroutines are used in data processing systems to reduce the amount of memory required and to simplify the coding or programming of the data processing system. However, the use of subroutines can cause time delays since return addresses and the contents of processor registers must be saved upon entering a subroutine so that processing can be resumed upon return from that subroutine. In many data processing systems, subroutines involve multiple main memory writes and reads with the resulting processor delay due to the disparity between memory access time and processor cycle time. In data processing systems which include a cache memory the delay is reduced by handling the necessary information for subroutine operations through the cache memory.
Subroutine information required to resume normal processing upon return from a subroutine is required only one time, i.e., upon return from the associated subroutine. When a cache memory is used for storing subroutine information, the subroutine information which has been read from the cache memory by the processor will not be required again but remains in the cache memory until removed by the replacement algorithm used in the cache memory. Accordingly, cache memory operation is not as efficient as possible.